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PT6524 LCD Driver IC
DESCRIPTION
PT6524 is a General Purpose LCD Driver IC utilizing CMOS Technology specially designed for electronic tuners controlled by microcontroller. It can drive up to a maximum of 204 segment outputs and can control up to 12 general purpose output ports. Pin assignments and application circuit are optimized for easy PCB layout and cost saving advantages.
FEATURES
* * * * * * * * * CMOS Technology Up to 4 Common and 51 Segment Drivers Up to 204 LCD Segments Up to 12 General Purpose Output Ports 1/4 Duty - 1/2 Bias or 1/4 Duty - 1/3 Bias Drive Technique No Decoder Intervention Necessary to Display the Data Power Saving Mode provided RC Oscillation Circuit Available in 64 pins, QFP or LQFP
APPLICATION
* Frequency Display for Electronic Tuners
BLOCK DIAGRAM
Tel: 886-66296288Fax: 886-29174598 http://www.princeton.com.tw2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6524
APPLICATION CIRCUIT 1
1/2 BIAS (NORMAL PANELS)
Note: C 0.047F
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PT6524
APPLICATION CIRCUIT 2
1/2 BIAS (LARGE PANELS)
Notes: 1. C 0.047F 2. 10K R 1K
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PT6524
APPLICATION CIRCUIT 3
1/3 BIAS (NORMAL PANELS)
Note: C 0.047F
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PT6524
APPLICATION CIRCUIT 4
1/3 BIAS (LARGE PANELS)
Notes: 1. 10K R 1K 2. C 0.047F
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PT6524
ORDER INFORMATION
Valid Part Number PT6524 PT6524LQ Package Type 64 Pin, QFP 64 Pin, LQFP Top Code PT6524 PT6524LQ
PIN CONFIGURATION
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PIN DESCRIPTION
Pin Name SG1/P1 ~ SG12/P12 SG13 ~ SG51 COM1 ~ COM4 VDD VDD1 I/O O O O Description Segment Driver Output/General Purpose Output Ports Segment Driver Output Pins Common Driver Output Pins Power Supply Power Supply This pin is used to apply a 2/3 LCD Drive Bias Voltage. If the 1/2 Bias Drive Technique is used, this pin must be short to VDD2. Power Supply This pin is used to apply a 1/3 LCD Drive Bias Voltage. If the 1/2 Bias Drive Technique is used, this pin must be short to VDD1. Ground Oscillation Input / Output Pin Display OFF Control Pin If this pin is set to "LOW" (VSS), the display is forced to turn OFF. Output driver pins -- SG1/P1 to SG12/P12, SG13 to SG51, COM1 to COM4 are set to "LOW". If this pin is set to "HIGH" (VDD), the display is turned ON. (see Note) Chip Enable Pin Clock Input Pin Data Input Pin Pin No. 1 ~ 12 13 ~ 51 52 ~55 56 57
VDD2 VSS OSC /INH CE CLK DI
I/O I I I I
58 59 60 61 62 63 64
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PT6524
INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below:
INPUT PIN: CLK, CE, DI, /INH
OUTPUT PIN: COM1 TO COM4, SG13 TO SG51
OUTPUT PIN: SG1/P1 to SG12/P12
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PT6524
FUNCTION DESCRIPTION
CONTROL DATA BITS
CU: NORMAL MODE CURRENT DRAIN CONTROL DATA BIT
This control bit is used to select the current drain (either Normal Current Drain or Low Current Drain) in the Normal Mode. Please refer to the table below. CU 0 1 Current Drain (under the Normal Mode) Normal Current Drain (IDD2, IDD3, IDD4 & IDD5) Low Current Drain (IDD6, IDD7, IDD8 & IDD9)
It should be noted that when the Low Current Drain is selected by setting the CU to "1", the output waveforms of the common and segment driver are easily distorted since the capacity to supply the current to the LCD panel from the Common and Segment Pins is less than capacity under the Normal Current Drain (CU = "0").
P0 TO P3: SEGMENT/ GENERAL PURPOSE OUTPUT PORT SELECT BITS
These control bits are used to select the function of the SG1/P1 to SG12/P12 output pins (either Segment Output Pins or General Purpose Output Pins). Please refer to the table below. Control Data Output Pins SG1/ SG2/ SG3/ SG4/ SG5/ SG6/ SG7/ SG8/ SG9/ SG10 SG11 SG12/ P0 P1 P2 P3 P1 P2 P3 P4 P5 P6 P7 P8 P9 /P10 /P11 P12 0 0 0 0 SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 0 0 1 P1 SG2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 0 1 0 P1 P2 SG3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 0 1 1 P1 P2 P3 SG4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 1 0 0 P1 P2 P3 P4 SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 1 0 1 P1 P2 P3 P4 P5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 0 1 1 0 P1 P2 P3 P4 P5 P6 SG7 SG8 SG9 SG10 SG11 SG12 0 1 1 1 P1 P2 P3 P4 P5 P6 P7 SG8 SG9 SG10 SG11 SG12 1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8 SG9 SG10 SG11 SG12 1 0 0 1 P1 P2 P3 P4 P5 P6 P7 P8 P9 SG10 SG11 SG12 1 0 1 0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 SG11 SG12 1 0 1 1 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 SG12 1 1 0 0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 When the General Purpose Output Port Function is selected, the correspondence between the output pins and the respective display data is given in the table below. Output Pin Corresponding Display Data Output Pin Corresponding Display Data SG1/P1 D1 SG7/P7 D25 SG2/P2 D5 SG8/P8 D29 SG3/P3 D9 SG9/P9 D33 SG4/P4 D13 SG10/P10 D37 SG5/P5 D17 SG11/P11 D41 SG6/P6 D21 SG12/P12 D45 When the General Purpose Output Port Function is selected, the respective output pin is output a "HIGH" level when it corresponding display data is set to "1". Likewise, it will output a "LOW" level, if its corresponding display data is set to "0". For example, SG4/P4 is used as a General Purpose Output Port, if its corresponding display data - D13 is set to "1", then SG4/P4 will output "HIGH" level. Likewise, if D13 is set to "0", then SG4/P4 will output "LOW" level.
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PT6524
DR: BIAS DRIVE TECHNIQUR CONTROL DATA BIT
This control bit is used to select either 1/2 Bias drive or 1/3 Bias Drive Technique. Please refer to the table below. DR Bias Drive Technique 0 1/3 1 1/2
SC: SEGMENT ON / OFF CONTROL DATA BIT
This control bit is used to select the state of the segment driver output pins. Please refer to the table below. SC Display State 0 ON 1 OFF
BU: NORMAL / POWER SAVING MODE SELECT BIT
This control bit is used to select either the Normal Mode or the Power Saving Mode. Please refer to the table below. BU Mode Remarks 0 Normal Mode The oscillation circuit stops, the common and segment output pins are set to "LOW" level. It must be noted that the output pins - SG1/P1 to SG12/P12 1 Power Saving Mode may be used as General Purpose Output Ports by setting the control bits - P0 to P3.
DISPLAY CONTROL AND THE /INH PIN
When power is initialized, the internal data of PT6524 (that is, display data - D1 to D204 and the control data) are not defined. Irrelevant displays caused by the undefined internal data can be prevented by using the following procedures. The /INH pin must be set to "LOW" at the same the as the power is applied to turn OFF the display. Doing this will set the output pins - SG1/P1 to SG12/P12, SG13 to SG51 and COM1 to COM4 to "LOW" level. While the /INH pin is held at "LOW" level, the microcontroller must send the serial data. Then the application can set the /INH pin to "HIGH". Please refer to the figure below.
Notes: 1. t1 = determined by the value of C and R. 2. tc = 10us (minimum)
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PT6524
DISPLAY DATA AND THE OUTPUT PIN CORRESPONDENCE
Output Pin SG1/P1 SG2/P2 SG3/P3 SG4/P4 SG5/P5 SG6/P6 SG7/P7 SG8/P8 SG9/P9 SG10/P10 SG11/P11 SG12/P12 SG13 SG14 SG15 SG16 SG17 SG18 SG19 SG20 SG21 SG22 SG23 SG24 SG25 SG26 SG27 SG28 SG29 SG30 SG31 SG32 SG33 SG34 SG35 SG36 SG37 SG38 SG39 SG40 SG41 SG42 SG43 SG44 SG45 SG46 SG47 SG48 SG49 SG50 SG51 V1.3 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D201 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D202 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D203 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 D204 11
Note: The Segment Output Port function is assumed to be selected for the output pins - SG1/P1 to SG12/P12.
PT6524
To illustrate further, the states of the S21 output pin is given in the table below. Display Data State of SG21 Output Pin D81 D82 D83 D84 0 0 0 0 LCD Segments corresponding to COM1 to COM4 are OFF. 0 0 0 1 LCD Segment corresponding to COM4 is ON. 0 0 1 0 LCD Segment corresponding to COM3 is ON. 0 0 1 1 LCD Segments corresponding to COm3 and COM4 are ON. 0 1 0 0 LCD Segment corresponding to COM2 is ON. 0 1 0 1 LCD Segments corresponding to COM2 and COM4 are ON. 0 1 1 0 LCD Segments corresponding to COM2 and COM3 are ON. 0 1 1 1 LCD Segments corresponding to COM2, COM3 and COM4 are ON. 1 0 0 0 LCD Segment corresponding to COM1 is ON. 1 0 0 1 LCD Segments corresponding to COM1 and COM4 are ON. 1 0 1 0 LCD Segments corresponding to COM1 and COM3 are ON. 1 0 1 1 LCD Segments corresponding to COM1, COM3 and COM4 are ON. 1 1 0 0 LCD Segments corresponding to COM1 and COM2 are ON. 1 1 0 1 LCD Segments corresponding to COM1, COM2, and COM4 are ON. 1 1 1 0 LCD Segments corresponding to COM1, COM2, and COM3 are ON. 1 1 1 1 LCD Segments corresponding to COM1 and COM 4 are ON.
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PT6524
SERIAL DATA INPUT
CONDITION 1: WHEN CLK IS TERMINATED AT "LOW" LEVEL
Notes: 1. Address: 41H 2. D1 to D204: Display Data 3. CU: Normal Mode Current Drain Control Data 4. P0 to P3: Segment Output Port/General Purpose Port Control Data Bit 5. DR: 1/2 or 1/3 Bias Drive Control Data Bit 6. SC: Segment ON /OFF Control Data Bit 7. BU: Normal Mode/Power-Saving Mode Control Data Bit
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PT6524
CONDITION 2: WHEN CLK IS TERMINATED AT "HIGH" LEVEL
Notes: 1. Address: 41H 2. D1 to D204: Display Data 3. CU: Normal Mode Current Drain Control Data 4. P0 to P3: Segment Output Port / General Purpose Port Control Data Bit 5. DR: 1/2 or 1/3 Bias Drive Control Data Bit 6. SC: Segment ON /OFF Control Data Bit 7. BU: Normal Mode/Power-Saving Mode Control Data Bit
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PT6524
SERIAL DATA TRANSFER
SERIAL DATA TRANSFER FOR 157 OR MORE SEGMENTS
SERIAL DATA TRANSFER FOR LESS THAN 157 SEGMENTS
Under a serial data transfer whereby less than 157 segments are used, 64, 128 or 192 bits of serial data must be transmitted depending on the actual number of segments used. The display data bits D1 to D52 and the control data must always sent. Please refer to the figure below.
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PT6524
1/4 DUTY, 1/2 BIAS DRIVE TECHNIQUE
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PT6524
1/4 DUTY, 1/3 BIAS DRIVE TECHNIQUE
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PT6524
ABSOLUTE MAXIMUM RATING
(Unless otherwise stated, Ta=25, Vss=0V) Parameter Symbol Maximum Supply Voltage VDDmax VIN1 Input Voltage VIN2 Output Voltage Output Current Allowable Power Dissipation Operating Temperature Storage Temperature VOUT IOUT1 IOUT2 IOUT3 PDmax Topr Tstg Condition VDD CE, CLK, DI, /INH OSC, VDD1, VDD2 OSC, SG1 to SG51, COM1 to COM4, P1 to P12 SG1 to SG51 COM1 to COM4 P1 to P12 Ta=85 Rating -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 300 3 5 200 -40 to +85 -65 to +150 Unit V V V V A mA mA mW
ALLOWABLE OPERATING RANGE
(Unless otherwise stated, Ta=25, Vss=0V) Parameter Symbol Condition Supply Voltage VDD VDD VDD1 VDD1 Input Voltage VDD2 VDD2 High Level Input Voltage VIH CE, CLK, DI, /INH Low Level Input Voltage VIL CE, CLK, DI, /INH Recommended External Rosc OSC Resistance Recommended External Cosc OSC Capacitance Guaranteed Oscillation fosc OSC Range Data Setup Time tds CLK, DI (see Note) Data Hold Time tdh CLK, DI (see Note) CE Wait Time tcp CE, CLK (see Note) CE Setup Time tcs CE, CLK (see Note) CE Hold Time tch CE, CLK (see Note) High Level Clock Pulse CLK (see Note) tH Width Low Level Clock Pulse CLK, (see Note) tL Width Rise Time tr CE, CLK, DI (see Note) Fall Time tf CE, CLK, DI (see Note) /INH Switching Time tc /INH, CE (see Note) Min. 3.0 0.8VDD 0 25 160 160 160 160 160 160 160 10 Typ. 2/3VDD 1/3VDD 270 100 50 160 160 Max. 6.0 VDD VDD 6.0 0.2VDD 100 Unit V V V V V K pF KHz ns ns ns ns ns ns ns ns ns s
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PT6524
Notes: 1. When CLK is terminated at "LOW" level
2. When CLK is terminated at "HIGH" level.
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PT6524
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, Ta=25, Vss=0V) Parameter Symbol Conditions Hysteresis VH CE, CLK, DI, /INH High Level Input Current IIH CE, CLK, DI, /INH, VI=6.0V Low Level Input Current IIL CE, CLK, DI, /INH, VI=0V VOH1 SG1 to SG51; Io=-20A High Level Output VOH2 COM1 to COM2; Io=-100A Voltage VOH3 P1 to P12; Io=-1mA VOL1 SG1 to SG51; Io=20A Low Level Output VOL2 COM1 to COM4; Io=100A Voltage VOL3 P1 to P12; Io=1mA COM1 to COM4 VMID1 1/2 Bias, Io=100A SG1 to SG51 VMID2 1/3 Bias, Io=20A Middle Level Output Sg1 to SG51 VMID3 Voltage 1/3 Bias, Io=20A COM1 to COM4 VMID4 1/3 Bias, Io=100A COM1 to COM4 VMID5 1/3 Bias, Io=100A OSC Oscillation Frequency Fosc Rosc=270K, osc=100pF IDD1 Power Saving Mode VDD=3.0V; Outputs open IDD2 1/2 Bias, fosc=50KHz, Control Data CU=0 VDD=6V; Outputs Open IDD3 1/2 Bias, fosc=50KHZ Control Data CU=0 VDD=3.0V; Outputs Open IDD4 1/3 Bias, fosc=50KHz Control Data CU=0 VDD=6.0V; Outputs Open IDD5 1/3 Bias, fosc=50KHz Control Data CU=0 Current Drain VDD=3.0V;Outputs Open IDD6 1/2 Bias, fosc=50KHz Control Data CU=1 VDD=6.0V;Outputs Open IDD7 1/2 Bias, fosc=50KHz Control Data CU=1 VDD=3.0V; Outputs Open IDD8 1/3 Bias, fosc=50KHz Control Data CU=1 VDD=6.0 Outputs Open IDD9 1/3 Bias, fosc=50KHz Control Data CU=1 Min. -5.0 VDD-1.0 VDD-1.0 VDD-1.0 1/2VDD-1.0 2/3VDD-1.0 1/3VDD-1.0 2/3VDD-1.0 1/3VDD-1.0 40 Typ. 0.1VDD 50 70 200 80 250 30 130 40 Max. 5.0 1.0 1.0 1.0 1/2VDD+1.0 2/3VDD+1.0 1/3VDD+1.0 2/3VDD+1.0 1/3VDD+1.0 60 5 140 400 160 500 60 260 80 Unit V A A V V V V V V V V V V V KHz A A A A A A A A
-
150
300
A
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PT6524
Note: The Bias Voltage Generation Divider built-into the VDD1 and VDD2 are not included. Please refer to the diagram below.
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PT6524
PACKAGE INFORMATION
64 PINS, QFP (BODY SIZE: 14MM X 14MM, PITCH: 0.80MM)
Symbol A A1 A2 b c D D1 E E1 e L L1 Notes: 1. Refer to JEDEC MC-022BE 2. Unit: mm V1.3
Min. 0.00 1.90 0.29 0.11
0.65 0
Nom. 0.35 17.20 BSC 14.00 BSC 17.20 BSC 14.00 BSC 0.80 BSC 1.00 REF -
Max. 3.15 0.25 2.905 0.41 0.23
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PT6524
64 PINS, LQFP (BODY SIZE: 10MM X 10MM, PITCH: 0.50MM, THK BODY: 1.40MM)
Symbol A A1 A2 b c D D1 E E1 e L L1
Min. 0.05 1.35 0.17 0.09
Nom. Max. 1.60 0.15 1.40 1.45 0.22 0.27 0.20 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.50 BSC 0.42 0.60 0.75 1.00 REF 0 3.5 7
Notes: 1. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. 3. Unit: mm 4. Refer to JEDEC MS-026BCB
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PT6524 IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw
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